| Gate 1 | a(x) ≥ hmin. The admissibility condition applied to the specification itself. It is evaluated before any outcome exists and determines whether reliable decoding is possible (§5.1). |
| Gate 2 | R ∈ Aρ. The directional admissibility condition applied to the outcome once Gate 1 has been cleared. It determines whether the outcome belongs to the user-declared evaluable domain and is therefore constitutive of evaluability (§5.2). |
| Gate 3 | ‖ΠQ (R)‖ ≥ θQ. The institutional quality sufficiency condition applied to the outcome once Gate 2 has been cleared. It determines whether the outcome satisfies the institution’s quality requirement (§5.3); risk-adjusted and component-floor forms in Appendix C. |
| What the later gates receive | R, if a(x) ≥ hmin; ⊥, if a(x) < hmin. The later gates operate only on an admissible outcome and receive the absence marker otherwise (§5.1). |
| ⊥ | Marker for the absence of an admissible outcome. It indicates that reliable decoding has not occurred and therefore that no admissible outcome stands. It does not denote the system’s output (§5.1). |